Approximation of stroked higher-order curved segments by quadratic bèzier curve segments

ABSTRACT

One embodiment of the present invention sets forth a technique for subdividing stroked higher-order curved segments into quadratic Bèzier curve segments. Path stroking may be accelerated when a GPU or other processor is configured to perform the subdivision operations. Cubic Bèzier path segments are subdivided into quadratic Bèzier curve segments and other lower-order segments at key features. The quadratic Bèzier curve segments approximate the cubic Bèzier path segments. A variance metric is computed for each quadratic Bèzier curve segment, and when the variance metric indicates that the quadratic Bèzier curve segment deviates by more than a threshold from the corresponding portion of the cubic Bèzier path segment, the quadratic Bèzier curve segment is further subdivided. The path composed of the quadratic Bèzier curve segments is then stroked by rendering hull geometry that encloses the path.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority benefit to United States provisionalpatent application titled, “Path Rendering,” filed on May 21, 2010 andhaving Ser. No. 61/347,359 (Attorney Docket Number NVDA/SC-10-0110-US0).This related application is also hereby incorporated by reference in itsentirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to graphics processing and morespecifically to approximation of stroked higher-order curved segments byquadratic segments.

2. Description of the Related Art

Path rendering is a style of resolution-independent two-dimensional (2D)rendering, often called “vector graphics,” that is the basis for anumber of important rendering standards such as PostScript, Java 2D,Apple's Quartz 2D, OpenVG, PDF, TrueType fonts, OpenType fonts,PostScript fonts, Scalable Vector Graphics (SVG) web format, Microsoft'sSilverlight and Adobe Flash for interactive web experiences, Open XMLPaper Specification (OpenXPS), drawings in Office file formats includingPowerPoint, Adobe Illustrator illustrations, and more.

Path rendering is resolution-independent meaning that a scene isdescribed by paths without regard to the pixel resolution of theframebuffer. This is in contrast to the resolution-dependent nature ofso-called bitmapped graphics. Whereas bitmapped images exhibit blurredor pixilated appearance when zoomed or otherwise transformed, scenesspecified with path rendering can be rendered at different resolutionsor otherwise transformed without blurring the boundaries of filled orstroked paths.

Sometimes the term vector graphics is used to mean path rendering, butpath rendering is a more specific approach to computer graphics. Whilevector graphics could be any computer graphics approach that representsobjects (typically 2D) in a resolution-independent way, path renderingis a much more specific rendering model with salient features thatinclude path filling, path stroking, path masking, compositing, and pathsegments specified as Bèzier curves.

FIG. 1A is a prior art scene composed of a sequence of paths. In pathrendering, a 2D picture or scene such as that shown in FIG. 1A isspecified as a sequence of paths. Each path is specified by a sequenceof path commands and a corresponding set of scalar coordinates. Pathrendering is analogous to how an artist draws with pens and brushes. Apath is a collection of sub-paths. Each sub-path (also called atrajectory) is a connected sequence of line segments and/or curvedsegments. Each sub-path may be closed, meaning the sub-path's start andterminal points are the same location so the stroke forms a loop;alternatively, a sub-path can be open, meaning the sub-path's start andterminal points are distinct.

When rendering a particular path, the path may be filled, stroked, orboth. As shown in FIG. 1A, the paths constituting the scene are stroked.When a path is both filled and stroked, typically the stroking operationis done immediately subsequent to the filling operation so the strokingoutlines the filled region. Artists tend to use stroking and fillingtogether in this way to help highlight or offset the filled region sotypically the stroking is done with a different color than the filling.

FIG. 1B is the sequence of paths shown in FIG. 1A with only filling.Filling is the process of coloring or painting the set of pixels“inside” the closed sub-paths of a path. Filling is similar to the way achild would “color in between the lines” of a coloring book. If asub-path within a path is not closed when such a sub-path is filled, thestandard practice is to force the sub-path closed by connecting its endand start points with an implicit line segment, thereby closing thesub-path, and then filling that resulting closed path.

While the meaning of “inside a path” generally matches the intuitivemeaning of this phrase, path rendering formalizes this notion with whatis called a fill-rule. The intuitive sense of “inside” is sufficient aslong as a closed sub-path does not self-intersect itself. However if asub-path intersects itself or another sub-path or some sub-paths arefully contained within other sub-paths, what it means to be inside oroutside the path needs to be better specified.

Stroking is distinct from filling and is more analogous to tracing oroutlining each sub-path in a path as if with a pen or marker. Strokingoperates on the perimeter or boundary defined by the path whereasfilling operates on the path's interior. Unlike filling, there is norequirement for the sub-paths within a path to be closed for stroking.For example, the curve of a letter “S” could be stroked without havingto be closed though the curve of the letter “O” could also be stroked.

FIG. 1C is a prior art scene composed of the sequence of paths from FIG.1A with the stroking from FIG. 1A and the filling from FIG. 1B. FIG. 1Cshows how filling and stroking are typically combined in a pathrendering scene for a complete the scene. Both stroking and filling areintegral to the scene's appearance.

Traditionally, graphics processing units (GPUs) have included featuresto accelerate 2D bitmapped graphics and three-dimensional (3D) graphics.In today's systems, nearly all path rendering is performed by a centralprocessing unit (CPU) performing scan-line rendering with noacceleration by a GPU. GPUs do not directly render curved primitives sopath rendering primitives such as Bèzier segments and partial ellipticalarcs must be approximated by lots of tiny triangles when a GPU is usedto render the paths. Constructing the required tessellations of a paththat is approximated by many short connected line segments can create asubstantial CPU burden. The triangles or other polygons resulting fromtessellation are then rendered by the GPU. Because GPUs are so fast atrasterizing triangles, tessellating paths into polygons that can then berendered by GPUs is an obvious approach to GPU-accelerating pathrendering.

Tessellation is a fragile, often quite sequential, process that requiresglobal inspection of the entire path. Tessellation depends on dynamicdata structures to sort, search, and otherwise juggle the incrementalsteps involved in generating a tessellation. Path rendering makes thisprocess considerably harder by permitting curved path segments as wellas allowing path segments to self-intersect, form high genus topologies,and be unbounded in size.

A general problem with using a GPU to render paths is unacceptably poorantialiasing quality when compared to standard CPU-based methods. Theproblem is that GPUs rely on point sampling for rasterization oftriangular primitives with only 1 to 8 samples (often 4) per pixel.CPU-based scan-line methods typically rely on 16 or more samples perpixel and can accumulate coverage over horizontal spans.

Animating or editing paths is costly because it requires re-tessellatingthe entire path since the tessellation is resolution dependent, and ingeneral it is very difficult to prove a local edit to a path will notcause a global change in the tessellation of the path. Furthermore, whencurved path segments are present and the scaling of the path withrespect to pixel space changes appreciably (zooming in say), the curvedpath segments may need to be re-subdivided and re-tessellation is likelyto be necessary.

Additionally, compositing in path rendering systems typically requiresthat pixels rasterized by a filled or stroked path are updatedonce-and-only-once per rasterization of the path. This requirement meansnon-overlapping tessellations are required. So for example, a crosscannot be tessellated as two overlapping rectangles but rather must berendered by the outline of the cross, introducing additional verticesand primitives. In particular, this means the sub-paths of a path cannotbe processed separately without first determining that no two sub-pathsoverlap. These requirements, combined with the generally fragile andsequential nature of tessellation algorithms make path tessellationparticularly expensive. Because of the expense required in generatingtessellations, it is very tempting and pragmatic to cache tessellations.Unfortunately such tessellations are much less compact than the originalpath representations, particularly when curved path segments areinvolved. Consequently, a greater amount of data must be stored to cachepaths after tessellation compared with storing the paths prior totessellation.

Conventional stroking has been performed by approximating paths intosub-pixel linear segments and then tracing the segments with a circlehaving a diameter equal to a stroke width. Offset curves are generatedat the boundary of the stroked path. These offset curves are typicallyof much higher degree of complexity compared with the linear segmentsthat are traced to generate the stroked path. Determining whether or noteach pixel is inside or outside of a stroked path to generate thestroking is mathematically complex. Identification of the pixels to bestroked is equivalent to identifying pixels that are within half of thestroke width of any point along the path to be stroked. Morespecifically, the pixels to be stroked are within half of the strokewidth measured along a line that is perpendicular to the tangent of thepath segment being stroked.

The tangent of a sub-path is not necessarily well-defined at junctionsbetween path segments. So additional rules are needed to determine whathappens at and in the vicinity of such junctions as well as what happensat the terminal (start and end) points of sub-paths. Therefore strokingspecifies further stroking rules to handle these situations.

In standard path rendering systems, paths are specified as a sequence ofcubic and quadratic (non-rational) Bèzier curve segments, partialelliptical arcs, and line segments. While more mathematically complexpath segments representations could be used to specify paths, inpractice, existing standards limit themselves to the aforementioned pathsegment types.

Path filling and stroking use the same underlying path specification.For filling, this means the resulting piece-wise boundaries to be filledmay be up to third-order (in the case of cubic Bèzier segments) orrational second-order (in the case of partial elliptical arcs). Fillingthese curved boundaries of Bèzier curves and arcs is clearly harder thanfilling the standard polygonal primitives in conventional polygonal 2Dor 3D rendering where the boundaries (edges) of the polygonal primitives(usually triangles) are all first-order, being linear segments, andoften required to be convex. Filling (and stroking) are also harder thanconventional line and convex polygon rasterization because paths areunbounded in their complexity whereas line segments and triangles aredefined by just 2 or 3 points respectively. A path may contain just asingle path segment or it could contain thousands or more.

The boundaries of stroked paths are actually substantially higher orderthan the third-order segments. The offset curve of non-rational(second-order) quadratic and (third-order) cubic Bèzier curves areeighth- and tenth-order curves respectively. This high order makes exactdetermination and evaluation of the resulting offset curves for suchBèzier segments intractable for use in direct rendering. In other words,it is quite unreasonable to try to determine exactly the boundaryrepresentation of such offset curves and then simply fill them. For thisreason, various techniques have been developed to approximate offsetcurves with sequences of Bèzier, arc, or line segments. Theseapproximate stroke boundaries may then be filled.

FIG. 1D illustrates prior art exterior stroke offset curves for variousstroke widths of a generating path 200. Observe in FIG. 1D how as thestroke width radius increases, the respective offset curves 207 for eachdifferent stroke width exhibit self-intersections 222 and cusps 223. Theexterior stroke offset curves are higher-order curves compared with thegenerating path 200. FIG. 1E illustrates interior stroke offset curvesfor various stroke widths of a generating path 221. The interior strokebounding curves are higher-order curves compared with the generatingpath 221. Observe in FIG. 1E how offset curves with a small radius leavea topological hole inside the generating path 221. As the radiusincreases with each wider radius, the hole splits into two holes. Thelargest radius shown fills in the hole completely. These changes in thegenus of the region bounded by offset curves and the emergence oftangent discontinuities on the boundary of wide offset curves illustratesome of the difficulties associated with exact rasterization of strokedpaths.

The idea that stroking is “harder” than filling is a bit unintuitivewhen filling and stroking are considered on an intuitive, artisticlevel. An artist typically thinks of stroking as a form of sketching oroutlining whereas filling requires “coloring in between the lines.” Intypical rasterized path rendering scenes, most of pixels tend to bepainted by filling rather than stroking so there is a sense that moreeffort is expended to perform the filling simply because more pixelswere painted by filling.

This intuition seems to be further validated when one appreciates thatevaluating the fill-rule required for proper filling requires a globalview of the entire path. Just because a pixel appears to be inscribedwithin a particular loop of a path does not mean the pixel should bepainted because the path might contain another loop with the oppositewinding order that all inscribes that pixel. Certainly there are veryintricate paths where determining whether a pixel filled by such anintricate path is quite involved; however most paths, in practice, areoften reasonably simple (meaning non-self-intersecting and topologicallygenus zero).

However this naïve intuition that filling might be easier is misleading;proper stroking is hard because of the mathematical complexity of theboundary of a path's stroke compared to a path's fill. Whileapproximations to the actual stroke boundary can reduce this complexity,such approximations have associated costs due to inaccuracy and theresulting expansion in the number of primitives that must be both storedand processed to render such approximated strokes. For example, thestroke of a quadratic Bèzier segment can be represented with just thesegment's 3 control points (along with the per-path stroke width)whereas an approximation of this stroked boundary with line segmentsmight require dozens or even hundreds of triangles to tessellateapproximately the stroked region. Indeed the quality of suchtessellations depends on the projection of the curved segment toscreen-space; this means rendering the same stroked curve at differentresolutions would necessitate different tessellations.

Accordingly, what is needed in the art is an improved system and methodfor approximating stroked higher-order curved segments using quadraticsegments.

SUMMARY OF THE INVENTION

One embodiment of the present invention sets forth a technique forapproximating higher-order curved segments with quadratic Bèzier curvesegments. Cubic Bèzier path segments are approximated with quadraticBèzier curve segments and other lower-order segments. A variance metricis computed for each quadratic Bèzier curve segment, and when thevariance metric indicates that the quadratic Bèzier curve segmentdeviates by more than a threshold from the corresponding portion of thecubic Bèzier path segment, the cubic Bèzier curve segment is subdividedinto multiple quadratic Bèzier curve segments. The path composed of thequadratic Bèzier curve segments may then be stroked by rendering hullgeometry that encloses the path. A technique for rasterizing strokedquadratic Bèzier segments is described in patent application titled,“Point Containment for Quadratic Bèzier Strokes,” filed on Mar. 25, 2011and having Ser. No. 13/071,904 (Attorney Docket No.NVDA/SC-10-0112-US0-US1).

Various embodiments of a method of the invention for approximatingstroked higher-order curved segments with quadratic Bèzier curvesegments include receiving a path including a cubic Bèzier path segmentand computing endpoint positions and tangents for the cubic Bèzier pathsegment. An approximating quadratic Bèzier curve segment is fitted tothe endpoint positions and tangents computed for the cubic Bèzier pathsegment and the method determines whether the approximating quadraticBèzier curve segment is accurate based on a variance metric. Otherembodiments may apply a similar approximating approach to partialelliptical arcs. An approximated path that includes the approximatingquadratic Bèzier curve segment is stroked.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentinvention can be understood in detail, a more particular description ofthe invention, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

FIG. 1A is a prior art scene composed of a sequence of stroked paths;

FIG. 1B is the fill for the prior art scene shown in FIG. 1A;

FIG. 1C is the prior art scene of FIG. 1A with the fill of FIG. 1B andthe stroked sequence of paths;

FIG. 1D illustrates prior art exterior stroke bounding curves forvarious stroke widths of a generating path;

FIG. 1E illustrates prior art interior stroke bounding curves forvarious stroke widths of a generating path;

FIG. 2A is a block diagram illustrating a computer system configured toimplement one or more aspects of the present invention;

FIG. 2B is a block diagram of a parallel processing subsystem for thecomputer system of FIG. 2A, according to one embodiment of the presentinvention;

FIG. 3A is a block diagram of a GPC within one of the PPUs of FIG. 2B,according to one embodiment of the present invention;

FIG. 3B is a block diagram of a partition unit within one of the PPUs ofFIG. 2B, according to one embodiment of the present invention;

FIG. 3C is a block diagram of a portion of the SPM of FIG. 3A, accordingto one embodiment of the present invention;

FIG. 4 is a conceptual diagram of a graphics processing pipeline thatone or more of the PPUs of FIG. 2B can be configured to implement,according to one embodiment of the present invention;

FIG. 5A illustrates a path that may be represented as a sequence ofquadratic Bèzier path segments and stroked, according to one embodimentof the invention;

FIG. 5B illustrates a generating cubic Bèzier curve, control points, andcorresponding inside and outside edges of the stroked generating cubicBèzier curve, according to one embodiment of the invention;

FIG. 5C illustrates a quadratic Bèzier curve segment that isapproximates a generating cubic Bèzier curve, according to oneembodiment of the invention;

FIG. 5D illustrates the quadratic Bèzier curve segments of FIG. 5C andconservative bounding hull geometry, according to one embodiment of theinvention;

FIG. 6A is a flow diagram of method steps for stroking a path includingcubic Bèzier segments, according to one embodiment of the presentinvention; and

FIG. 6B is a flow diagram of method steps for processing cubic pathsegment parameters as performed in a method step shown in FIG. 8A,according to one embodiment of the present invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth toprovide a more thorough understanding of the present invention. However,it will be apparent to one of skill in the art that the presentinvention may be practiced without one or more of these specificdetails. In other instances, well-known features have not been describedin order to avoid obscuring the present invention.

System Overview

FIG. 2A is a block diagram illustrating a computer system 100 configuredto implement one or more aspects of the present invention. Computersystem 100 includes a central processing unit (CPU) 102 and a systemmemory 104 communicating via an interconnection path that may include amemory bridge 105. Memory bridge 105, which may be, e.g., a Northbridgechip, is connected via a bus or other communication path 106 (e.g., aHyperTransport link) to an I/O (input/output) bridge 107. I/O bridge107, which may be, e.g., a Southbridge chip, receives user input fromone or more user input devices 108 (e.g., keyboard, mouse) and forwardsthe input to CPU 102 via path 106 and memory bridge 105. A parallelprocessing subsystem 112 is coupled to memory bridge 105 via a bus orother communication path 113 (e.g., a PCI Express, Accelerated GraphicsPort, or HyperTransport link); in one embodiment parallel processingsubsystem 112 is a graphics subsystem that delivers pixels to a displaydevice 110 (e.g., a conventional CRT or LCD based monitor). A systemdisk 114 is also connected to I/O bridge 107. A switch 116 providesconnections between I/O bridge 107 and other components such as anetwork adapter 118 and various add-in cards 120 and 121. Othercomponents (not explicitly shown), including USB or other portconnections, CD drives, DVD drives, film recording devices, and thelike, may also be connected to I/O bridge 107. Communication pathsinterconnecting the various components in FIG. 2A may be implementedusing any suitable protocols, such as PCI (Peripheral ComponentInterconnect), PCI-Express, AGP (Accelerated Graphics Port),HyperTransport, or any other bus or point-to-point communicationprotocol(s), and connections between different devices may use differentprotocols as is known in the art.

In one embodiment, the parallel processing subsystem 112 incorporatescircuitry optimized for graphics and video processing, including, forexample, video output circuitry, and constitutes a graphics processingunit (GPU). In another embodiment, the parallel processing subsystem 112incorporates circuitry optimized for general purpose processing, whilepreserving the underlying computational architecture, described ingreater detail herein. In yet another embodiment, the parallelprocessing subsystem 112 may be integrated with one or more other systemelements, such as the memory bridge 105, CPU 102, and I/O bridge 107 toform a system on chip (SoC).

It will be appreciated that the system shown herein is illustrative andthat variations and modifications are possible. The connection topology,including the number and arrangement of bridges, the number of CPUs 102,and the number of parallel processing subsystems 112, may be modified asdesired. For instance, in some embodiments, system memory 104 isconnected to CPU 102 directly rather than through a bridge, and otherdevices communicate with system memory 104 via memory bridge 105 and CPU102. In other alternative topologies, parallel processing subsystem 112is connected to I/O bridge 107 or directly to CPU 102, rather than tomemory bridge 105. In still other embodiments, I/O bridge 107 and memorybridge 105 might be integrated into a single chip. Large embodiments mayinclude two or more CPUs 102 and two or more parallel processing systems112. The particular components shown herein are optional; for instance,any number of add-in cards or peripheral devices might be supported. Insome embodiments, switch 116 is eliminated, and network adapter 118 andadd-in cards 120, 121 connect directly to I/O bridge 107.

FIG. 2B illustrates a parallel processing subsystem 112, according toone embodiment of the present invention. As shown, parallel processingsubsystem 112 includes one or more parallel processing units (PPUs) 202,each of which is coupled to a local parallel processing (PP) memory 204.In general, a parallel processing subsystem includes a number U of PPUs,where U≧1. (Herein, multiple instances of like objects are denoted withreference numbers identifying the object and parenthetical numbersidentifying the instance where needed.) PPUs 202 and parallel processingmemories 204 may be implemented using one or more integrated circuitdevices, such as programmable processors, application specificintegrated circuits (ASICs), or memory devices, or in any othertechnically feasible fashion.

Referring again to FIG. 2A, in some embodiments, some or all of PPUs 202in parallel processing subsystem 112 are graphics processors withrendering pipelines that can be configured to perform various tasksrelated to generating pixel data from graphics data supplied by CPU 102and/or system memory 104 via memory bridge 105 and bus 113, interactingwith local parallel processing memory 204 (which can be used as graphicsmemory including, e.g., a conventional frame buffer) to store and updatepixel data, delivering pixel data to display device 110, and the like.In some embodiments, parallel processing subsystem 112 may include oneor more PPUs 202 that operate as graphics processors and one or moreother PPUs 202 that are used for general-purpose computations. The PPUsmay be identical or different, and each PPU may have its own dedicatedparallel processing memory device(s) or no dedicated parallel processingmemory device(s). One or more PPUs 202 may output data to display device110 or each PPU 202 may output data to one or more display devices 110.

In operation, CPU 102 is the master processor of computer system 100,controlling and coordinating operations of other system components. Inparticular, CPU 102 issues commands that control the operation of PPUs202. In some embodiments, CPU 102 writes a stream of commands for eachPPU 202 to a pushbuffer (not explicitly shown in either FIG. 2A or FIG.2B) that may be located in system memory 104, parallel processing memory204, or another storage location accessible to both CPU 102 and PPU 202.PPU 202 reads the command stream from the pushbuffer and then executescommands asynchronously relative to the operation of CPU 102.

Referring back now to FIG. 2B, each PPU 202 includes an I/O(input/output) unit 205 that communicates with the rest of computersystem 100 via communication path 113, which connects to memory bridge105 (or, in one alternative embodiment, directly to CPU 102). Theconnection of PPU 202 to the rest of computer system 100 may also bevaried. In some embodiments, parallel processing subsystem 112 isimplemented as an add-in card that can be inserted into an expansionslot of computer system 100. In other embodiments, a PPU 202 can beintegrated on a single chip with a bus bridge, such as memory bridge 105or I/O bridge 107. In still other embodiments, some or all elements ofPPU 202 may be integrated on a single chip with CPU 102.

In one embodiment, communication path 113 is a PCI-EXPRESS link, inwhich dedicated lanes are allocated to each PPU 202, as is known in theart. Other communication paths may also be used. An I/O unit 205generates packets (or other signals) for transmission on communicationpath 113 and also receives all incoming packets (or other signals) fromcommunication path 113, directing the incoming packets to appropriatecomponents of PPU 202. For example, commands related to processing tasksmay be directed to a host interface 206, while commands related tomemory operations (e.g., reading from or writing to parallel processingmemory 204) may be directed to a memory crossbar unit 210. Hostinterface 206 reads each pushbuffer and outputs the work specified bythe pushbuffer to a front end 212.

Each PPU 202 advantageously implements a highly parallel processingarchitecture. As shown in detail, PPU 202(0) includes a processingcluster array 230 that includes a number C of general processingclusters (GPCs) 208, where C≧1. Each GPC 208 is capable of executing alarge number (e.g., hundreds or thousands) of threads concurrently,where each thread is an instance of a program. In various applications,different GPCs 208 may be allocated for processing different types ofprograms or for performing different types of computations. For example,in a graphics application, a first set of GPCs 208 may be allocated toperform patch tessellation operations and to produce primitivetopologies for patches, and a second set of GPCs 208 may be allocated toperform tessellation shading to evaluate patch parameters for theprimitive topologies and to determine vertex positions and otherper-vertex attributes. The allocation of GPCs 208 may vary dependent onthe workload arising for each type of program or computation.

GPCs 208 receive processing tasks to be executed via a work distributionunit 200, which receives commands defining processing tasks from frontend unit 212. Processing tasks include indices of data to be processed,e.g., surface (patch) data, primitive data, vertex data, and/or pixeldata, as well as state parameters and commands defining how the data isto be processed (e.g., what program is to be executed). Workdistribution unit 200 may be configured to fetch the indicescorresponding to the tasks, or work distribution unit 200 may receivethe indices from front end 212. Front end 212 ensures that GPCs 208 areconfigured to a valid state before the processing specified by thepushbuffers is initiated.

When PPU 202 is used for graphics processing, for example, theprocessing workload for each patch is divided into approximately equalsized tasks to enable distribution of the tessellation processing tomultiple GPCs 208. A work distribution unit 200 may be configured toproduce tasks at a frequency capable of providing tasks to multiple GPCs208 for processing. By contrast, in conventional systems, processing istypically performed by a single processing engine, while the otherprocessing engines remain idle, waiting for the single processing engineto complete its tasks before beginning their processing tasks. In someembodiments of the present invention, portions of GPCs 208 areconfigured to perform different types of processing. For example a firstportion may be configured to perform vertex shading and topologygeneration, a second portion may be configured to perform tessellationand geometry shading, and a third portion may be configured to performpixel shading in screen space to produce a rendered image. Intermediatedata produced by GPCs 208 may be stored in buffers to allow theintermediate data to be transmitted between GPCs 208 for furtherprocessing.

Memory interface 214 includes a number D of partition units 215 that areeach directly coupled to a portion of parallel processing memory 204,where D≧1. As shown, the number of partition units 215 generally equalsthe number of DRAM 220. In other embodiments, the number of partitionunits 215 may not equal the number of memory devices. Persons skilled inthe art will appreciate that DRAM 220 may be replaced with othersuitable storage devices and can be of generally conventional design. Adetailed description is therefore omitted. Render targets, such as framebuffers or texture maps may be stored across DRAMs 220, allowingpartition units 215 to write portions of each render target in parallelto efficiently use the available bandwidth of parallel processing memory204.

Any one of GPCs 208 may process data to be written to any of the DRAMs220 within parallel processing memory 204. Crossbar unit 210 isconfigured to route the output of each GPC 208 to the input of anypartition unit 215 or to another GPC 208 for further processing. GPCs208 communicate with memory interface 214 through crossbar unit 210 toread from or write to various external memory devices. In oneembodiment, crossbar unit 210 has a connection to memory interface 214to communicate with I/O unit 205, as well as a connection to localparallel processing memory 204, thereby enabling the processing coreswithin the different GPCs 208 to communicate with system memory 104 orother memory that is not local to PPU 202. In the embodiment shown inFIG. 2B, crossbar unit 210 is directly connected with I/O unit 205.Crossbar unit 210 may use virtual channels to separate traffic streamsbetween the GPCs 208 and partition units 215.

Again, GPCs 208 can be programmed to execute processing tasks relatingto a wide variety of applications, including but not limited to, linearand nonlinear data transforms, filtering of video and/or audio data,modeling operations (e.g., applying laws of physics to determineposition, velocity and other attributes of objects), image renderingoperations (e.g., tessellation shader, vertex shader, geometry shader,and/or pixel shader programs), and so on. PPUs 202 may transfer datafrom system memory 104 and/or local parallel processing memories 204into internal (on-chip) memory, process the data, and write result databack to system memory 104 and/or local parallel processing memories 204,where such data can be accessed by other system components, includingCPU 102 or another parallel processing subsystem 112.

A PPU 202 may be provided with any amount of local parallel processingmemory 204, including no local memory, and may use local memory andsystem memory in any combination. For instance, a PPU 202 can be agraphics processor in a unified memory architecture (UMA) embodiment. Insuch embodiments, little or no dedicated graphics (parallel processing)memory would be provided, and PPU 202 would use system memoryexclusively or almost exclusively. In UMA embodiments, a PPU 202 may beintegrated into a bridge chip or processor chip or provided as adiscrete chip with a high-speed link (e.g., PCI-EXPRESS) connecting thePPU 202 to system memory via a bridge chip or other communication means.

As noted above, any number of PPUs 202 can be included in a parallelprocessing subsystem 112. For instance, multiple PPUs 202 can beprovided on a single add-in card, or multiple add-in cards can beconnected to communication path 113, or one or more of PPUs 202 can beintegrated into a bridge chip. PPUs 202 in a multi-PPU system may beidentical to or different from one another. For instance, different PPUs202 might have different numbers of processing cores, different amountsof local parallel processing memory, and so on. Where multiple PPUs 202are present, those PPUs may be operated in parallel to process data at ahigher throughput than is possible with a single PPU 202. Systemsincorporating one or more PPUs 202 may be implemented in a variety ofconfigurations and form factors, including desktop, laptop, or handheldpersonal computers, servers, workstations, game consoles, embeddedsystems, and the like.

Processing Cluster Array Overview

FIG. 3A is a block diagram of a GPC 208 within one of the PPUs 202 ofFIG. 2B, according to one embodiment of the present invention. Each GPC208 may be configured to execute a large number of threads in parallel,where the term “thread” refers to an instance of a particular programexecuting on a particular set of input data. In some embodiments,single-instruction, multiple-data (SIMD) instruction issue techniquesare used to support parallel execution of a large number of threadswithout providing multiple independent instruction units. In otherembodiments, single-instruction, multiple-thread (SIMT) techniques areused to support parallel execution of a large number of generallysynchronized threads, using a common instruction unit configured toissue instructions to a set of processing engines within each one of theGPCs 208. Unlike a SIMD execution regime, where all processing enginestypically execute identical instructions, SIMT execution allowsdifferent threads to more readily follow divergent execution pathsthrough a given thread program. Persons skilled in the art willunderstand that a SIMD processing regime represents a functional subsetof a SIMT processing regime.

Operation of GPC 208 is advantageously controlled via a pipeline manager305 that distributes processing tasks to streaming multiprocessors(SPMs) 310. Pipeline manager 305 may also be configured to control awork distribution crossbar 330 by specifying destinations for processeddata output by SPMs 310.

In one embodiment, each GPC 208 includes a number M of SPMs 310, whereM≧1, each SPM 310 configured to process one or more thread groups. Also,each SPM 310 advantageously includes an identical set of functionalexecution units (e.g., execution and load-store units—shown as Execunits 302 and LSUs 303 in FIG. 3C) that may be pipelined, allowing a newinstruction to be issued before a previous instruction has finished, asis known in the art. Any combination of functional execution units maybe provided. In one embodiment, the functional units support a varietyof operations including integer and floating point arithmetic (e.g.,addition and multiplication), comparison operations, Boolean operations(AND, OR, XOR), bit-shifting, and computation of various algebraicfunctions (e.g., planar interpolation, trigonometric, exponential, andlogarithmic functions, etc.); and the same functional-unit hardware canbe leveraged to perform different operations.

The series of instructions transmitted to a particular GPC 208constitutes a thread, as previously defined herein, and the collectionof a certain number of concurrently executing threads across theparallel processing engines (not shown) within an SPM 310 is referred toherein as a “warp” or “thread group.” As used herein, a “thread group”refers to a group of threads concurrently executing the same program ondifferent input data, with one thread of the group being assigned to adifferent processing engine within an SPM 310. A thread group mayinclude fewer threads than the number of processing engines within theSPM 310, in which case some processing engines will be idle duringcycles when that thread group is being processed. A thread group mayalso include more threads than the number of processing engines withinthe SPM 310, in which case processing will take place over consecutiveclock cycles. Since each SPM 310 can support up to G thread groupsconcurrently, it follows that up to G*M thread groups can be executingin GPC 208 at any given time.

Additionally, a plurality of related thread groups may be active (indifferent phases of execution) at the same time within an SPM 310. Thiscollection of thread groups is referred to herein as a “cooperativethread array” (“CTA”) or “thread array.” The size of a particular CTA isequal to m*k, where k is the number of concurrently executing threads ina thread group and is typically an integer multiple of the number ofparallel processing engines within the SPM 310, and m is the number ofthread groups simultaneously active within the SPM 310. The size of aCTA is generally determined by the programmer and the amount of hardwareresources, such as memory or registers, available to the CTA.

Each SPM 310 contains an L1 cache (not shown) or uses space in acorresponding L1 cache outside of the SPM 310 that is used to performload and store operations. Each SPM 310 also has access to L2 cacheswithin the partition units 215 that are shared among all GPCs 208 andmay be used to transfer data between threads. Finally, SPMs 310 alsohave access to off-chip “global” memory, which can include, e.g.,parallel processing memory 204 and/or system memory 104. It is to beunderstood that any memory external to PPU 202 may be used as globalmemory. Additionally, an L1.5 cache 335 may be included within the GPC208, configured to receive and hold data fetched from memory via memoryinterface 214 requested by SPM 310, including instructions, uniformdata, and constant data, and provide the requested data to SPM 310.Embodiments having multiple SPMs 310 in GPC 208 beneficially sharecommon instructions and data cached in L1.5 cache 335.

Each GPC 208 may include a memory management unit (MMU) 328 that isconfigured to map virtual addresses into physical addresses. In otherembodiments, MMU(s) 328 may reside within the memory interface 214. TheMMU 328 includes a set of page table entries (PTEs) used to map avirtual address to a physical address of a tile and optionally a cacheline index. The MMU 328 may include address translation lookasidebuffers (TLB) or caches which may reside within multiprocessor SPM 310or the L1 cache or GPC 208. The physical address is processed todistribute surface data access locality to allow efficient requestinterleaving among partition units. The cache line index may be used todetermine whether of not a request for a cache line is a hit or miss.

In graphics and computing applications, a GPC 208 may be configured suchthat each SPM 310 is coupled to a texture unit 315 for performingtexture mapping operations, e.g., determining texture sample positions,reading texture data, and filtering the texture data. Texture data isread from an internal texture L1 cache (not shown) or in someembodiments from the L1 cache within SPM 310 and is fetched from an L2cache, parallel processing memory 204, or system memory 104, as needed.Each SPM 310 outputs processed tasks to work distribution crossbar 330in order to provide the processed task to another GPC 208 for furtherprocessing or to store the processed task in an L2 cache, parallelprocessing memory 204, or system memory 104 via crossbar unit 210. ApreROP (pre-raster operations) 325 is configured to receive data fromSPM 310, direct data to ROP units within partition units 215, andperform optimizations for color blending, organize pixel color data, andperform address translations.

It will be appreciated that the core architecture described herein isillustrative and that variations and modifications are possible. Anynumber of processing units, e.g., SPMs 310 or texture units 315, preROPs325 may be included within a GPC 208. Further, while only one GPC 208 isshown, a PPU 202 may include any number of GPCs 208 that areadvantageously functionally similar to one another so that executionbehavior does not depend on which GPC 208 receives a particularprocessing task. Further, each GPC 208 advantageously operatesindependently of other GPCs 208 using separate and distinct processingunits, L1 caches, and so on.

FIG. 3B is a block diagram of a partition unit 215 within one of thePPUs 202 of FIG. 2B, according to one embodiment of the presentinvention. As shown, partition unit 215 includes a L2 cache 350, a framebuffer (FB) DRAM interface 355, and a raster operations unit (ROP) 360.L2 cache 350 is a read/write cache that is configured to perform loadand store operations received from crossbar unit 210 and ROP 360. Readmisses and urgent writeback requests are output by L2 cache 350 to FBDRAM interface 355 for processing. Dirty updates are also sent to FB 355for opportunistic processing. FB 355 interfaces directly with DRAM 220,outputting read and write requests and receiving data read from DRAM220.

In graphics applications, ROP 360 is a processing unit that performsraster operations, such as stencil, z test, blending, and the like, andoutputs pixel data as processed graphics data for storage in graphicsmemory. In some embodiments of the present invention, ROP 360 isincluded within each GPC 208 instead of partition unit 215, and pixelread and write requests are transmitted over crossbar unit 210 insteadof pixel fragment data.

The processed graphics data may be displayed on display device 110 orrouted for further processing by CPU 102 or by one of the processingentities within parallel processing subsystem 112. Each partition unit215 includes a ROP 360 in order to distribute processing of the rasteroperations. In some embodiments, ROP 360 may be configured to compress zor color data that is written to memory and decompress z or color datathat is read from memory.

Persons skilled in the art will understand that the architecturedescribed in FIGS. 2A, 2B, 3A, and 3B in no way limits the scope of thepresent invention and that the techniques taught herein may beimplemented on any properly configured processing unit, including,without limitation, one or more CPUs, one or more multi-core CPUs, oneor more PPUs 202, one or more GPCs 208, one or more graphics or specialpurpose processing units, or the like, without departing the scope ofthe present invention.

In embodiments of the present invention, it is desirable to use PPU 202or other processor(s) of a computing system to execute general-purposecomputations using thread arrays. Each thread in the thread array isassigned a unique thread identifier (“thread ID”) that is accessible tothe thread during its execution. The thread ID, which can be defined asa one-dimensional or multi-dimensional numerical value controls variousaspects of the thread's processing behavior. For instance, a thread IDmay be used to determine which portion of the input data set a thread isto process and/or to determine which portion of an output data set athread is to produce or write.

A sequence of per-thread instructions may include at least oneinstruction that defines a cooperative behavior between therepresentative thread and one or more other threads of the thread array.For example, the sequence of per-thread instructions might include aninstruction to suspend execution of operations for the representativethread at a particular point in the sequence until such time as one ormore of the other threads reach that particular point, an instructionfor the representative thread to store data in a shared memory to whichone or more of the other threads have access, an instruction for therepresentative thread to atomically read and update data stored in ashared memory to which one or more of the other threads have accessbased on their thread IDs, or the like. The CTA program can also includean instruction to compute an address in the shared memory from whichdata is to be read, with the address being a function of thread ID. Bydefining suitable functions and providing synchronization techniques,data can be written to a given location in shared memory by one threadof a CTA and read from that location by a different thread of the sameCTA in a predictable manner. Consequently, any desired pattern of datasharing among threads can be supported, and any thread in a CTA canshare data with any other thread in the same CTA. The extent, if any, ofdata sharing among threads of a CTA is determined by the CTA program;thus, it is to be understood that in a particular application that usesCTAs, the threads of a CTA might or might not actually share data witheach other, depending on the CTA program, and the terms “CIA” and“thread array” are used synonymously herein.

FIG. 3C is a block diagram of the SPM 310 of FIG. 3A, according to oneembodiment of the present invention. The SPM 310 includes an instructionL1 cache 370 that is configured to receive instructions and constantsfrom memory via L1.5 cache 335. A warp scheduler and instruction unit312 receives instructions and constants from the instruction L1 cache370 and controls local register file 304 and SPM 310 functional unitsaccording to the instructions and constants. The SPM 310 functionalunits include N exec (execution or processing) units 302 and Pload-store units (LSU) 303.

SPM 310 provides on-chip (internal) data storage with different levelsof accessibility. Special registers (not shown) are readable but notwriteable by LSU 303 and are used to store parameters defining each CTAthread's “position.” In one embodiment, special registers include oneregister per CTA thread (or per exec unit 302 within SPM 310) thatstores a thread ID; each thread ID register is accessible only by arespective one of the exec unit 302. Special registers may also includeadditional registers, readable by all CTA threads (or by all LSUs 303)that store a CTA identifier, the CTA dimensions, the dimensions of agrid to which the CTA belongs, and an identifier of a grid to which theCTA belongs. Special registers are written during initialization inresponse to commands received via front end 212 from device driver 103and do not change during CTA execution.

A parameter memory (not shown) stores runtime parameters (constants)that can be read but not written by any CTA thread (or any LSU 303). Inone embodiment, device driver 103 provides parameters to the parametermemory before directing SPM 310 to begin execution of a CTA that usesthese parameters. Any CTA thread within any CTA (or any exec unit 302within SPM 310) can access global memory through a memory interface 214.Portions of global memory may be stored in the L1 cache 320.

Local register file 304 is used by each CTA thread as scratch space;each register is allocated for the exclusive use of one thread, and datain any of local register file 304 is accessible only to the CTA threadto which it is allocated. Local register file 304 can be implemented asa register file that is physically or logically divided into P lanes,each having some number of entries (where each entry might store, e.g.,a 32-bit word). One lane is assigned to each of the N exec units 302 andP load-store units LSU 303, and corresponding entries in different lanescan be populated with data for different threads executing the sameprogram to facilitate SIMD execution. Different portions of the lanescan be allocated to different ones of the G concurrent thread groups, sothat a given entry in the local register file 304 is accessible only toa particular thread. In one embodiment, certain entries within the localregister file 304 are reserved for storing thread identifiers,implementing one of the special registers.

Shared memory 306 is accessible to all CTA threads (within a singleCTA); any location in shared memory 306 is accessible to any CTA threadwithin the same CTA (or to any processing engine within SPM 310). Sharedmemory 306 can be implemented as a shared register file or sharedon-chip cache memory with an interconnect that allows any processingengine to read from or write to any location in the shared memory. Inother embodiments, shared state space might map onto a per-CTA region ofoff-chip memory, and be cached in L1 cache 320. The parameter memory canbe implemented as a designated section within the same shared registerfile or shared cache memory that implements shared memory 306, or as aseparate shared register file or on-chip cache memory to which the LSUs303 have read-only access. In one embodiment, the area that implementsthe parameter memory is also used to store the CTA ID and grid ID, aswell as CTA and grid dimensions, implementing portions of the specialregisters. Each LSU 303 in SPM 310 is coupled to a unified addressmapping unit 352 that converts an address provided for load and storeinstructions that are specified in a unified memory space into anaddress in each distinct memory space. Consequently, an instruction maybe used to access any of the local, shared, or global memory spaces byspecifying an address in the unified memory space.

The L1 Cache 320 in each SPM 310 can be used to cache private per-threadlocal data and also per-application global data. In some embodiments,the per-CTA shared data may be cached in the L1 cache 320. The LSUs 303are coupled to a uniform L1 cache 375, the shared memory 306, and the L1cache 320 via a memory and cache interconnect 380. The uniform L1 cache375 is configured to receive read-only data and constants from memoryvia the L1.5 Cache 335.

Approximating Stroked Curved Segments

Path stroking has an associated “stroke width” that defines the regionthat is included in the stroke when a circle having a diameter of thestroke width is moved along the path segment. The path segment isconsidered a generating curve and the circle generates an inside offsetcurve and an outside offset curve as the circle moves along the pathsegment. Mathematical computation of the inside and the outside offsetcurves is difficult. Because stroking is an important operation for manyapplication programs that produce 2D images, it is desirable toaccelerate stroking operations. In one embodiment, a GPU, such as thePPU 202, may be used to perform functions to accelerate strokingoperations. Importantly, tessellation of the path segments is avoided.Instead, a path is approximated by quadratic Bèzier curve segments orsegments of lower complexity, e.g., arcs, line segments, and the like.

The GPU-accelerated stroking technique for rasterizing stroked quadraticBèzier segments described in patent application titled, “PointContainment for Quadratic Bèzier Strokes,” filed on Mar. 25, 2011 andhaving Ser. No. 13/071,904 (Attorney Docket No. NVDA/SC-10-0112-US0-US1)typically perform approximately 1 to 2 orders of magnitude more fragmentprocessing operations per sample than comparable GPU-acceleratedtechniques for filling paths. This relative expense is justified becauseit results in fewer approximations and a more compact andresolution-independent representation from which to render strokedpaths. The observation that more rendered pixels are filled than strokedin typical path rendering scenes with both types of path rendering alsohelps balance the relatively higher per-sample cost of stroking tofilling.

FIG. 5A illustrates a generating curve 500 that may be approximated by asequence of quadratic Bèzier path segments and stroked, according to oneembodiment of the invention. A stroke width having a constant strokeradius 543 defines a corresponding inside offset curve 542 and acorresponding outside offset curve 546 of the stroked generating curve500 that are separated from the generating curve 500 by the constantdistance of the stroke radius 543. First, the generating curve 500 isapproximated by quadratic Bèzier path segments, partial circles, andline segments. Approximating a path with quadratic Bèzier curvesegments, partial circles, and/or line segments produces a geometry setthat is suitable for stroking rendered paths containing higher-ordercurved segments, such as cubic Bèzier and partial elliptical arc pathsegments, without tessellating the path.

More specifically, a stroking engine approximates the higher-ordercurved segments into quadratic Bèzier curves so that the initial andterminal tangents are matched by the resulting sequence of quadraticBèzier segments, partial circles, and line segments and the continuityof the tangents is also preserved at each shared endpoint. When anapproximating quadratic Bèzier curve does not accurately represent theoriginating higher-order curve segment of the path, the stroke enginedivides the higher-order curve segment into multiple quadratic Bèzierpath segments. The stroke engine limits the subdivision into pathsegments based on the stroke width, so that the stroke boundary does notexpose the boundary of the generating curve. In order to maintaingeometrically important features of the curve and continuity of thetangents, key features such as the self-intersection that occurs at thekey feature location 520 of the generating curve 500 are identifiedduring the subdivision process. The generating curve 500 is subdividedinto two or more quadratic Bèzier curve segments at the key featurelocation 520. Other key features include cusps and points of maximumcurvature. When the key feature is a cusp within some segment of thegenerating curve, generating a partial circle centered at the cusplocation ensures the curve's stroke contains all the points within astroke radius of this cusp.

The quadratic Bèzier curve segments, partial circles, and line segmentsgenerated during the subdivision process to approximate the generatingcurve 500 are processed to determine whether or not points lie withinthe stroke region of each quadratic Bèzier curve segment, arc, or linesegment. Rather than computing the inside and outside offset curves, afunction is evaluated for each point that may be within the strokeregion that is bounded by the inside offset curve 542 and the outsideoffset curve 546. The function is specific to the point, so that eachpoint has a respective function. Points that lie within the strokeregion are then stroked to produce a stroked path. In the case of a pathconsisting of multiple segments, a point belongs to the path's stroke ifthe point is within the stroke of any segment belonging to the path.

Bèzier curves are defined by control points. In the 2D content of pathrendering, each control point is a 2D position. Curved path segments fora path may be generated by path commands for quadratic Bèzier curves,cubic Bèzier curves, and partial elliptical arcs.

A quadratic Bèzier curve is specified by 3 control points and a cubicBèzier curve is specified by 4 control points. The QUADRATICTO commanduses the terminal position of the prior command as its initial controlpoint (x0,y0) and then 4 associated coordinates form the two new (x1,y1)and (x2,y2) control points. The quadratic Bèzier curve starts at (x0,y0)heading towards (x1,y1) and ends at (x2,y2) as if coming from (x1,y1).Despite (x1,y1) providing the initial tangent direction when startingfrom (x0,y0) and terminating at (x2,y2), the resulting curve does notpass through (x1,y1); for this reason, (x1,y1) is known as anextrapolating control point while (x0,y0) and (x2,y2) are known asinterpolating control points.

The CUBICTO command is similar to the QUADRATICTO command but generatesa cubic Bèzier curve. Such a curve is specified by 4 control points. TheCUBICTO command uses the terminal position of the prior command as itsinitial control point (x0,y0) and then 6 associated coordinates form the3 new (x1,y1), (x2,y2), and (x3,y3) control points. The cubic Bèziercurve starts at (x0,y0) heading towards (x1,y1) and ends at (x3,y3) asif coming from (x2,y2). While a quadratic Bèzier curve has a singleextrapolating control point, cubic Bèzier curves have two extrapolatingcontrol points, (x1,y1) and (x2,y2). A cubic Bèzier curve has thefreedom, unlike a quadratic Bèzier curve, to specify arbitrary initialand terminal tangent directions for its end-points. This control makescubic Bèzier curves popular with artists. This additional control comesfrom the curve being described by a third-order bivariate polynomialequation instead of a second-order equation in the case of a quadraticBèzier curve (and first-order in the case of line segments).

FIG. 5B illustrates a generating cubic Bèzier curve 540, control pointsC₀, C₁, C₂, and C₃, and corresponding inside and outside edges of thestroked generating cubic Bèzier curve, according to one embodiment ofthe invention.

The cubic Bèzier curve 540 with control points C₀, C₁, C₂, and C₃ can beapproximated by a quadratic Bèzier segment that shares the sameend-points positions (C₀ and C₃) and normalized tangents (T₀ and T₃). Inthis case, the quadratic Bèzier curve segment has the control points C₀,C_(mid), and C₃ where C_(mid) is

$\begin{matrix}{{C_{mid} = {C_{0} + {\frac{\begin{matrix}{C_{1} - C_{0}} \\T_{3}\end{matrix}}{\begin{matrix}T_{0} \\T_{3}\end{matrix}}\left( {C_{1} - C_{0}} \right)}}}{where}} & \left( {{equation}\mspace{14mu} 1} \right) \\{{T_{0} = \frac{C_{1} - C_{0}}{\sqrt{\left( {C_{1} - C_{0}} \right) \cdot \left( {C_{1} - C_{0}} \right)}}}{T_{3} = \frac{C_{3} - C_{2}}{\sqrt{\left( {C_{3} - C_{2}} \right) \cdot \left( {C_{3} - C_{2}} \right)}}}} & \left( {{equation}\mspace{14mu} 2} \right)\end{matrix}$

Notice these equations will result in division by zero if C₀ and C₁ areco-located, C₂ and C₃ are co-located, or T₀ and T₃ are coincident. Theseare all situations that can occur when 3 or more control points of thecubic Bèzier segment are collinear. In order to avoid these collinearsituations or very nearly collinear control points (i.e., within acollinear threshold), such cubic Bèzier segments should be replaced withline segments appropriately.

FIG. 5C illustrates a quadratic Bèzier curve segment 555 thatapproximates the generating cubic Bèzier curve shown in FIG. 5B,according to one embodiment of the invention. The quadratic Bèzier curvesegment 555 shares the same end-point positions (C₀ and C₃) andnormalized tangents (T₀ and T₃) as the generating cubic Bèzier curve 540and has the control points C₀, C_(mid), and C₃.

A variance metric V between the cubic Bèzier curve 540 and theapproximating quadratic Bèzier curve segment 555 with matching tangentend-points directions is computed as

$\begin{matrix}{V = \frac{\begin{matrix}{{C_{0} \cdot \left( {{2\; C_{0}} - {12\; C_{1}} - {9\; C_{2}} + {3\; C_{3}} + {14\; C_{mid}}} \right)} +} \\{{C_{1} \cdot \left( {{18\; C_{1}} + {27\; C_{2}} - C_{3} - {42\; C_{mid}}} \right)} +} \\{{C_{2} \cdot \left( {{18\; C_{2}} - {12\; C_{3}} - {42\; C_{mid}}} \right)} +} \\{{C_{3} \cdot \left( {{2\; C_{3}} + {14\; C_{mid}}} \right)} + {28\; {C_{mid} \cdot C_{mid}}}}\end{matrix}}{210}} & \left( {{equation}\mspace{14mu} 3} \right)\end{matrix}$

The variance is the square of the deviation between the cubic curve andits approximating quadratic form. Hence a deviation value computed asthe square root of V divided by an approximation of the arc length ofthe cubic Bèzier curve 540 is comparable to the displacement of theapproximating quadratic Bèzier curve segment 555 compared with the cubicBèzier curve 540. Other variance metrics are possible, but equation 3minimizes in a least squares sense the difference between correspondingparametric positions on the cubic Bèzier segment and its approximatingquadratic Bèzier segment. The deviation value may be compared to thestroke width to quantify the accuracy of the approximating quadraticBèzier curve segment 555. When the deviation value is not within atolerance threshold, the cubic Bèzier curve segment 540 is subdividedinto two cubic Bèzier curve segments using the well-known De Casteljaualgorithm for splitting Bèzier curves. The two new cubic Bèzier curvesegments are again fitted to their respective approximate quadraticBèzier segment (essentially treating them as a new generating cubicBèzier curve 540. This process of subdivision continues until thevariance metric is satisfied or some maximum subdivision limit isreached. The geometric tangent (G1) continuity at a shared endpoint ofthe two new quadratic Bèzier curve segments is maintained; this ensureseven under extremely magnified or zoomed viewing there is never anyapparent loss of curved appearance along the curved stroke segment'sboundary, in contrast to the prior art's use of line segments. In oneembodiment, a cubic Bèzier curve may be subdivided into a number ofquadratic Bèzier curve segments based on the size of the stroke width.For example, the number may increase as the stroke width decreases anddecrease as the stroke width increases.

Following subdivision into approximating quadratic Bèzier curvesegments, a point containment algorithm may be used to determine whethera point is “inside” or “outside” the stroke region of a path. Applying apoint containment algorithm to each and every sample that is potentiallywithin the boundary defined by the path or stroked boundary isfundamental to the process of stroking a rendered path.

For each quadratic Bèzier path segment, the stroking engine generates aconservative hull polygon that completely encloses a stroke region ofthe quadratic Bèzier path segment. FIG. 5D illustrates the quadraticBèzier curve segment 555 of FIG. 5C and conservative bounding hullgeometry 550, according to one embodiment of the invention. The strokingengine then computes a set of derived values from each quadratic Bèzierpath segment and the stroke width to facilitate an efficient computationof nearest points on the quadratic Bèzier path segment to a point thatmay be within the stroke region. When a GPU is used to perform thestroking operations, the derived values may be stored in a texture ortexture buffer object and ordered to correspond with their respectivequadratic Bèzier curve segment's convex hull geometry. Miter join stylesbetween cubic Bèzier segments are added with conventional triangles.

The tangent of a sub-path is not necessarily continuous at junctionsbetween quadratic Bèzier curve segments. So additional rules are neededto determine what happens at and in the vicinity of such junctions aswell as what happens at the terminal (start and end) points ofsub-paths. Therefore stroking specifies further stroking rules to handlethese situations. A join style determines what happens at the junctionbetween two connected path segments. Typical join styles are round,miter, and bevel. An end-cap style indicates what happens at the endpoints of open (non-closed) sub-paths. Typical end-cap styles are round,square, none, and triangle. If the sub-path is closed, the join style isused to connect the initial and terminal segments rather than using endcaps.

Therefore, points may belong to the path's stroke based on additionalend-cap and join-style point containment tests. Round end-cap andjoin-style tests depend on whether the point is within r units of thepath's end-points or segment join points. The miter and beveljoin-styles depend on the normalized tangent directions of the initialor terminal points of the path. The miter and bevel join-styles dependon the two normalized tangent directions when two path segments join ata segment join point. For a mitered join, if the cosine of the anglebetween the tangent directions exceeds the miter-limit, the miter istreated as either a bevel or truncated miter.

In addition to the hull geometry bounding the quadratic Bèzier curvesegments, the stroking engine also collects or generates a set ofpolygonal geometry for any square or triangular end-caps or mitered orbeveled join styles. The stroking engine also collects or generates aset of polygonal geometry for rounded stroking with associatedcoordinates to generate round end-caps, join styles, and hemi-circlesfor cusps of curved segments converted to line segments. This geometrymay include texture coordinates indicating vertex position relative tothe junction, end-point, or cusp. Cusps on segments of the generatingcurve are identified by the stroke engine as key features so that agenerating curve such as a cubic Bèzier segment containing a cusp willbe subdivided into quadratic cubic Bèzier curve segments on either sideof the cusp location. In order to include the full set of strokelocations within a stroke radius of such cusp locations, the strokeengine should add a partial circle centered at such cusp locations witha radius equal to the stroke radius to the curve's set of approximatinggeometry.

This same process can be used to decompose other higher-order curvedsegments into a sequence of quadratic Bèzier curves, partial circles,and line segments. In particular, partial elliptical arcs can bedecomposed by using the procedure above where the initial and terminalcontrol points are the start and stop positions of the arc and thetangent vectors of the arc at its end points can be used to generateextrapolating control points of a cubic Bèzier curve to serve as a proxyfor the arc. When splitting is required, the curve to split should bethe generating higher-order curve is required,

FIG. 6A is a flow diagram of method steps for stroking a path includingcubic Bèzier segments, according to one embodiment of the presentinvention. Although the method steps are described in conjunction withthe systems of FIGS. 2A, 2B, 3A, 3B, 3C, and 4, persons skilled in theart will understand that any system configured to perform the methodsteps, in any order, is within the scope of the inventions. The CPU 102or parallel processing subsystem 112 may be configured to stroke a paththat includes cubic Bèzier path segments, quadratic Bèzier pathsegments, line segments, and arcs. In one embodiment, the control pointsdefining each path segment are sorted before that path segment isprocessed to avoid the generation of approximating quadratic Bèziercurve segments that are dependent on the path segment direction; thisallows the path segment's stroke coverage to be invariant with directionof the stroke.

At step 605 a path segment including at least one cubic Bèzier pathsegment and stroke width is received by a path stroke engine and isapproximated by one or more quadratic Bèzier curve segments. The pathstroke engine may be embodied as an application program for execution byCPU 102 and/or parallel processing subsystem 112 or as circuitryconfigured to perform the method steps shown in FIG. 6A. The path strokeengine approximates cubic Bèzier curves and any higher order curves withquadratic Bèzier path segments and lower order path segments. The pathstroke engine determines if each path segment is a degenerate line orwithin an epsilon of being so, and if it is, the path segment isapproximated by a line segment. The path stroke engine also identifiesline segments (including line segments generated by the path strokeengine from degenerate lines) in the path and converts the identifiedline segments to rectangles. The path stroke engine also identifies pathcommands for curved segments other than cubic Bèzier segments andconverts such curved segments into an approximating sequence ofquadratic Bèzier curves, as described in conjunction with FIG. 6B.

At step 608 bounding hull geometry is generated by the path strokeengine for the quadratic Bèzier path segment. At step 610 per-quadraticBèzier path segment parameters computed by the path stroke engine. Theper-quadratic Bèzier path segment parameters may be computed by the CPU102. At step 615 the per-quadratic Bèzier path segment parameters areprocessed by the path stroke engine to determine which points are withinthe stroke region of each quadratic Bèzier path segment. The quadraticpath segment stroke containment involves solving of a particular cubicequation for each point so this computation is typically considerablymore expensive than the computations required to rasterize primitivesuch as rectangles or triangles. In one embodiment, the per-quadraticBèzier path segment parameters are processed by a combination of avertex shader program and a fragment shader program executed by theparallel processing subsystem 112.

At step 620 the path stroke engine determines if the path to be strokedincludes another quadratic Bèzier path segment, and, if so, then steps608, 610, and 615 are repeated. Otherwise, at step 625 stroking of thepath is complete. In one embodiment, the fragment shader is configuredto discard fragments not within the quadratic Bèzier path segment andthereby avoid writing a stencil buffer to indicate whether or not eachpixel is within the stroke region of a path. One or more geometric hullsthat conservatively cover the entire path are generated and rendered tofill the stroke region by writing the color buffer based on the stencilbuffer. In another embodiment, the stroke region is filled by writingthe color buffer as the hull geometry for each quadratic Bèzier pathsegment is processed.

FIG. 6B is a flow diagram of method steps for approximating a curvedpath including a cubic Bèzier segment into one or more quadratic Bèziercurve segments as performed in method step 605 shown in FIG. 6A,according to one embodiment of the present invention. At step 640 thepath stroke engine identifies key features of the path, e.g., locationsof cusps, self-intersections, and points of maximum curvature. At step642 the path stroke engine replaces collinear cubic Bèzier curvesegments with line segments. At step 645 the path stroke enginesubdivides the generating curve, i.e., path, at the key features.

At step 650 the path stroke engine fits quadratic Bèzier curve segmentsto the endpoints and tangents of the cubic Bèzier path segments includedin the curve. Importantly, geometric tangent continuity is maintainedduring the fitting of the quadratic Bèzier curve segments. At step 655the path stroke computes a variance metric and a deviation value thatquantifies the accuracy of an approximating quadratic Bèzier curvesegment. At step 660 the path stroke engine determines if the deviationvalue is within an acceptable tolerance based on the stroke width or amaximum number of subdivisions, and, if not, at step 665 the quadraticBèzier curve segment is subdivided and steps 650, 655, and 660 arerepeated for each new quadratic Bèzier curve segment. Otherwise, at step670 the path stroke engine determines if another approximating quadraticBèzier curve segment should be compared with the originating the cubicBèzier path segment for accuracy. If another quadratic Bèzier curvesegment should be compared, then the path stroke engine repeats steps655 and 660. Otherwise, all of the approximating quadratic Bèzier curvesegments meet the accuracy constraints and the path stroke engineproceeds to step 608.

Because the geometry set used to produce the stroked path isresolution-independent, the stroked path can be rasterized underarbitrary projective transformations without needing to revisit theconstruction of the geometry set. This resolution-independent propertyis unlike geometry sets built through a process of tessellating curvedregions into triangles; in such circumstances, sufficient magnificationof the filled path would reveal the tessellated underlying nature ofsuch a tessellated geometry set. The approximating quadratic Bèziercurve segments are also compact, meaning that the number of bytesrequired to represent the stroked path is linear with the number ofquadratic Bèzier path segments generated by original path. This propertydoes not generally hold for tessellated versions of stroked paths wherethe process of subdividing curved edges and introducing tessellatedtriangles typically increases the size of the resulting geometry setconsiderably.

One embodiment of the invention may be implemented as a program productfor use with a computer system. The program(s) of the program productdefine functions of the embodiments (including the methods describedherein) and can be contained on a variety of computer-readable storagemedia. Illustrative computer-readable storage media include, but are notlimited to: (i) non-writable storage media (e.g., read-only memorydevices within a computer such as CD-ROM disks readable by a CD-ROMdrive, flash memory, ROM chips or any type of solid-state non-volatilesemiconductor memory) on which information is permanently stored; and(ii) writable storage media (e.g., floppy disks within a diskette driveor hard-disk drive or any type of solid-state random-accesssemiconductor memory) on which alterable information is stored.

The invention has been described above with reference to specificembodiments. Persons skilled in the art, however, will understand thatvarious modifications and changes may be made thereto without departingfrom the broader spirit and scope of the invention as set forth in theappended claims. The foregoing description and drawings are,accordingly, to be regarded in an illustrative rather than a restrictivesense.

1. A method of approximating cubic Bèzier path segments, the methodcomprising: receiving a stroke width and a path including a cubic Bèzierpath segment; computing a first endpoint position, a second endpointposition, a first tangent at the first endpoint, and a second tangent atthe second endpoint for the cubic Bèzier path segment fitting anapproximating quadratic Bèzier curve segment to the endpoint positionsand tangents computed for the cubic Bèzier path segment; determiningwhether the approximating quadratic Bèzier curve segment is an accurateapproximation of the cubic Bèzier path segment based on a variancemetric; and stroking an approximated path including the approximatingquadratic Bèzier curve segment to fill a stroke region specified by thestroke width and the approximated path.
 2. The method of claim 1,wherein the stroking of the approximated path further comprisesconstructing a bounding hull geometry that encloses the approximatingquadratic Bèzier curve segment.
 3. The method of claim 2, wherein thestroking of the approximated path further comprises: rendering thebounding hull geometry; identifying sample points within the boundinghull geometry that are inside of a portion of the stroke region of theapproximating quadratic Bèzier curve segment; and writing a color bufferto fill pixels that are inside of the portion of the stroke region ofthe approximating quadratic Bèzier curve segment.
 4. The method of claim3, wherein the step of identifying sample points within the boundinghull geometry that are inside of the portion of the stroke region of theapproximating quadratic Bèzier curve segment comprises writing a stencilbuffer.
 5. The method of claim 1, wherein the variance metric is basedon the deviation between the cubic Bèzier path segment and theapproximating quadratic Bèzier curve segment.
 6. The method of claim 1,further comprising the steps of: identifying key features of the path;and subdividing the path at each key feature.
 7. The method of claim 6,wherein the key features include one or more of a cusp point, a point ofself-intersection, and a point of maximum curvature of the path.
 8. Themethod of claim 1, further comprising subdividing the cubic Bèzier pathsegment into two or more quadratic Bèzier curve segments when thevariance metric is not within a tolerance threshold.
 9. The method ofclaim 1, further comprising the step of fitting a second approximatingquadratic Bèzier curve segment to the first endpoint and a thirdendpoint while maintaining geometric tangent continuity with the firsttangent.
 10. The method of claim 1, further comprising replacing acollinear cubic Bèzier path segment of the path with a line segment. 11.A non-transitory computer-readable storage medium storing instructionsthat, when executed by a processor, cause the processor to approximatecubic Bèzier path segments, by performing the steps of: receiving astroke width and a path including a cubic Bèzier path segment; computinga first endpoint position, a second endpoint position, a first tangentat the first endpoint, and a second tangent at the second endpoint forthe cubic Bèzier path segment fitting an approximating quadratic Bèziercurve segment to the endpoint positions and tangents computed for thecubic Bèzier path segment; determining whether the approximatingquadratic Bèzier curve segment is an accurate approximation of the cubicBèzier path segment based on a variance metric; and stroking anapproximated path including the approximating quadratic Bèzier curvesegment to fill a stroke region specified by the stroke width and theapproximated path.
 12. The non-transitory computer-readable storagemedium of claim 11, wherein the stroking of the approximated pathfurther comprises constructing a bounding hull geometry that enclosesthe approximating quadratic Bèzier curve segment.
 13. The non-transitorycomputer-readable storage medium of claim 12, wherein the stroking ofthe approximated path further comprises: rendering the bounding hullgeometry; identifying sample points within the bounding hull geometrythat are inside of a portion of the stroke region of the approximatingquadratic Bèzier curve segment; and writing a color buffer to fillpixels that are inside of the portion of the stroke region of theapproximating quadratic Bèzier curve segment.
 14. The non-transitorycomputer-readable storage medium of claim 13, wherein the step ofidentifying sample points within the bounding hull geometry that areinside of the portion of the stroke region of the approximatingquadratic Bèzier curve segment comprises writing a stencil buffer. 15.The non-transitory computer-readable storage medium of claim 11, whereinthe variance metric is based on the deviation between the cubic Bèzierpath segment and the approximating quadratic Bèzier curve segment. 16.The non-transitory computer-readable storage medium of claim 11, furthercomprising the steps of: identifying key features of the path; andsubdividing the path at each key feature.
 17. The non-transitorycomputer-readable storage medium of claim 16, wherein the key featuresinclude one or more of a cusp point, a point of self-intersection, and apoint of maximum curvature of the path.
 18. The non-transitorycomputer-readable storage medium of claim 11, further comprisingsubdividing the cubic Bèzier path segment into two or more quadraticBèzier curve segments when the variance metric is not within a tolerancethreshold.
 19. The non-transitory computer-readable storage medium ofclaim 11, further comprising the step of fitting a second approximatingquadratic Bèzier curve segment to the first endpoint and a thirdendpoint while maintaining geometric tangent continuity with the firsttangent.
 20. A system for approximate cubic Bèzier path segments, thesystem comprising: a memory that is configured to store a stroke widthand a path including a cubic Bèzier path segment; and a processor thatis coupled to the memory and configured to: receive the stroke width andthe path including the cubic Bèzier path segment; compute a firstendpoint position, a second endpoint position, a first tangent at thefirst endpoint, and a second tangent at the second endpoint for thecubic Bèzier path segment fit an approximating quadratic Bèzier curvesegment to the endpoint positions and tangents computed for the cubicBèzier path segment; determine whether the approximating quadraticBèzier curve segment is an accurate approximation of the cubic Bèzierpath segment based on a variance metric; and stroke an approximated pathincluding the approximating quadratic Bèzier curve segment to fill astroke region specified by the stroke width and the approximated path.